Semiconductor device, and method for manufacturing the same

ABSTRACT

According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length. The first gate electrode comprises a crystal phase including a cubic crystal of NiSi 2  which has a lattice constant of 5.39 angstroms to 5.40 angstroms.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims the benefit of priority from theprior Japanese Patent Application No. 2006-63290, filed on Mar. 8, 2006;the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device having afield-effect transistor and to a method for manufacturing the same.

2. Description of Related Art

An ultra-integration silicon circuit is one of the basic technologiesthat are expected to support a future advanced information society.Higher functionality of an integrated circuit entails higher performanceof semiconductor elements which are constituent elements of theintegrated circuit; namely, a MOSFET (Metal-Oxide-SemiconductorField-Effect Transistor), a CMOSFET (Complementary MOSFET), and thelike. Higher performance of the element has been basically achievedaccording to a proportional scaling rule. However, various limitationson physical properties have recently come to pose difficulty inultra-miniaturization of an element which contribute to higherperformance.

For instance, problems are pointed out in connection with a gateelectrode using silicon; namely, manifestation of gate parasiticresistance caused by an increase in the operating speed of an element;an reduction in the effective capacitance of an insulation filmattributable to depletion of carriers in an interface of the insulationfilm; and variations in a threshold voltage attributable topunch-through of impurity additives into a channel region. In order tosolve these problems, metal gate materials are proposed.

One of the techniques for forming a metal gate electrode is a fullsilicide gate electrode technique for silicidizing all gate electrodeswith Ni or Co. The metal gate electrode requires a work function whichvaries according to a conductivity type, in order to operate a device atan optimal operation threshold voltage.

The reason for this is that the operation threshold voltage of the MIStransistor is modulated in accordance with variations in the workfunction (Φeff: an effective work function) of the gate electrode in theinterface between the gate electrode and the gate insulation film.Consequently, variations in the work function of the gate electrode inthe vicinity of the interface appear in unmodified form as variations inthe operation threshold voltage.

For instance, an attempt has been made to control the work function byadjusting the composition of silicide or a crystalline structure (Pleaserefer K. Takahashi et al., “Dual Workfunction Ni—Silicide/HfSiON GateStacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-node LSTP and LOP Devices,” IEDM 2004, 4.4.1-4.4.4 (hereinafter,referred to as “K. Takahashi et al.”), and N. Biswas et al.,“Workfunction turning of nickel silicide by co-sputtering nickel andsilicon,” Applied Physics Letters 87, 171908 (2005) “hereinafterreferred to as N. Biswas et al.”).

“K. Takahashi et al” discloses that a work function pertaining to thecomposition of NiSi₂ lies in the vicinity of about 4.4 eV and isappropriate for NMOS metal and that a work function pertaining to thecomposition of Ni₃Si lies in the vicinity of about 4.8 eV and isappropriate for PMOS metal. Consequently, these gate electrodesinvolving composition control show that the effective work function Φeffvaries by about 0.1 eV, which in turn induces variations in thethreshold voltage. This is considered to be attributable to the factthat the crystal phase of the gate electrode is not a single phase but amixed phase. Therefore, a single crystal phase is desired forcontrolling a work function.

In “K. Takahashi et al”, an attempt is made to induce a solid phasereaction in the interface between an Ni layer/a polycrystalline Si layerby varying a thickness ratio of an Ni layer/a polycrystalline Si layer(a composition ratio of NiSi) and a heat treatment temperature (rangingfrom 350° C. to 650° C.). The document describes that a mixed phasebetween the NiSi phase and an Ni₃Si phase, a mixed phase between theNi₃Si phase and an Ni₃₁Si₁₂ phase, and a mixed phase between the NiSiphase and the NiSi₂ phase are consequently generated. However, forinstance, when a single phase; e.g., an NiSi₂ phase, is formed, heattreatment at 650° C. or more is required. When silicidation is performedat such a high heat treatment temperature, the gate insulation film isdeteriorated, which in turn leads to an increase in a leakage current.

In JP-A-20005-129551, an attempt is made to change the ratio of thethickness of the Ni layer to the thickness of the polycrystalline Silayer, and to subject the layers to heat treatment at 400° C. in avacuum for one minute, thereby inducing a solid-phase reaction in theinterface between the Ni layer and the polycrystalline Si layer. Theresultantly-produced (Ni+Si) layer exhibits a work function from about4.4 eV to about 4.9 eV. However, the layer is considered to be a mixedphase consisting of Ni, Si and various species of NiSi), and the workfunction is expected to vary.

K. Takahashi et al. discloses that a work function from about 4.3 eV toabout 4.9 eV is exhibited when the silicide composition of NiSi_(x) isvaried. However, various crystal phases are observed from the result ofXRD (X-Ray Diffraction) of NiSi_(x), and a mixed phase is understood tobe formed.

Forming Ni silicide having a single-phase crystal structure isdifficult. Therefore, variations in threshold value cannot bediminished. Moreover, even when Ni silicide having a single-phasecrystal structure can be formed, a silicide reaction induced byhigh-temperature heat treatment is required, as in the case of the NiSi₂phase, which in turn causes an increase in leakage current.Consequently, Ni silicide of single phase cannot be used for gateelectrodes of both conductivity types (particularly type “n”).

A known approach is to silicidize single crystal Si and amorphous Si bylow-temperature heat treatment at 350° C. to 400° C., thereby generatingNiSi₂ (see O. Nakatsuka et al., “Low-Temperature Formation of EpitaxialNiSi₂ Layers with Solid-Phase Reaction in Ni/Ti/Si (001) Systems,”Japanese Journal of Applied Physics, Vol. 44, No. 5A, 2005, pp.2945-2947 (hereinafter, referred to as “O. Nakatsuka et al.”), and C.Hayzelder et al., “Silicide formation and silicide-mediatedcrystallization of nickel-implanted amorphous silicon thin films,” J.Appl. Physics. 73(12), 15 Jun. 1993, pp. 8279-8289.) (herein afterreferred to as “C. Hayzelder et al.”).

“O. Nakatsuka et al.” discloses that a multilayer consisting of Ni, athin layer of Ti, and monocrystal Si is subjected to heat treatment at350° C. for 30 minutes, to thus produce a multilayer structureconsisting of TiSi₂, NiSi₂, and monocrystal Si. However, an interfacebetween NiSi₂/monocrystal Si forms a (111) facet, which in turn inducesroughness.

“C. Hayzelder et al.” discloses that Ni is ion-implanted into amorphousSi and the amorphous Si is subjected to heat treatment at 400° C. forthree hours, to thus generate an NiSi₂ crystal seed. However, heattreatment which is as long as three hours is not realistic in processesfor manufacturing an LSI.

SUMMARY

The present invention has been made in view of the above circumstancesand provides a semiconductor device and a method for manufacturing thesame. According to an aspect of the present invention, a semiconductordevice can reduces variations in threshold value, as well as a methodfor manufacturing the same.

According to another aspect of the invention, a semiconductor devicecomprises: a N-channel MIS transistor comprising; a p-type semiconductorlayer; a first gate insulation layer formed on the p-type semiconductorlayer; a first gate electrode formed on the first gate insulation layer;and a first source-drain region formed in the p-type semiconductor layerwhere the first gate electrode is sandwiched along a direction of gatelength. The first gate electrode comprises a crystal phase including acubic crystal of NiSi₂ which has a lattice constant of 5.39 angstroms to5.40 angstroms.

According to another aspect of the invention, a semiconductor devicecomprises: a substrate; a N-channel MIS transistor comprising; a p-typesemiconductor layer formed on the substrate; a first gate insulationlayer formed on the p-type semiconductor layer; a first gate electrodeformed on the first gate insulation layer; and a first source-drainregion formed in the p-type semiconductor layer where the first gateelectrode is sandwiched along a direction of gate length; a P-channelMIS transistor comprising; a n-type semiconductor layer formed on thesubstrate; a second gate insulation layer formed on the n-typesemiconductor layer; a second gate electrode formed on the second gateinsulation layer. The second gate electrode comprises; a crystal phaseincluding at least one of a cubic crystal of Ni₃Si or a hexagonalcrystal of Ni₃₁Si₁₂; and a second source-drain region formed in then-type semiconductor layer where the second gate electrode sandwichedalong a direction of gate length. The first gate electrode comprises acrystal phase including a cubic crystal of NiSi₂ which has a latticeconstant of 5.39 angstroms to 5.40 angstroms.

According to another aspect of the invention, there is provided a methodfor manufacturing a semiconductor device comprising: forming a firstgate insulation layer on a p-type semiconductor layer; forming a firstpolycrystalline silicon layer on the first gate insulation layer;forming a first source-drain region on a surface of the p-typesemiconductor layer where the first polycrystalline silicon layer issandwiched; performing an ion implantation of Ni into the firstpolycrystalline silicon layer; performing a heat treatment for forming aNiSi₂ crystal nucleus in the first polycrystalline silicon layer at atemperature of 300° C. to 800° C.; forming on the first polycrystallinesilicon layer a first Ni layer whose thickness is 5/18 to ½ with respectto the thickness of the first polycrystalline silicon layer; andtransforming the first polycrystalline silicon layer into a crystalphase of NiSi₂ by performing a heat treatment for growing the NiSi₂crystal nucleus at a temperature of 300° C. to 600° C.

According to another aspect of the invention, there is provided a methodfor manufacturing a semiconductor device comprising: forming a firstgate insulation layer on a p-type semiconductor layer; forming a firstpolycrystalline silicon layer on the first gate insulation layer;forming a first source-drain region on a surface of the p-typesemiconductor layer where the first polycrystalline silicon layer issandwiched; forming a first Ti thin layer on the first polycrystallinesilicon layer; forming a first Ni layer on the first Ti thin layer; andperforming a heat treatment for transforming a multilayer (the first Nilayer/the first Ti thin layer/the first polycrystalline silicon layer)into a multilayer (a TiSi₂ crystal phase/an NiSi₂ crystal phase) at atemperature of 300° C. to 600° C.

According to another aspect of the invention, there is provided a methodfor manufacturing a semiconductor device, comprising: forming a firstgate insulation layer on a p-type semiconductor layer; forming a secondgate insulation layer on an n-type semiconductor layer; forming a firstpolycrystalline silicon layer on the first gate insulation layer;forming a second polycrystalline silicon layer on the second gateinsulation layer; forming a first source-drain region on a surface ofthe p-type semiconductor layer where the first polycrystalline siliconlayer is sandwiched; forming a second source-drain region on a surfaceof the n-type semiconductor layer where the second polycrystallinesilicon layer is sandwiched; forming a first Ti thin layer on the firstpolycrystalline silicon layer; forming a first Ni layer on the first Tithin layer; forming a second Ni layer, or a second Ti thin layer and thesecond Ni layer in order, on the second polycrystalline silicon layer;performing a first heat treatment at a temperature of 300° C. to 600°C., for transforming a multilayer (the first Ni layer/the first Ti thinlayer/the first polycrystalline silicon layer) into a first multilayer(a TiSi2 crystal phase/an NiSi2 crystal phase); and performing a secondheat treatment for forming a Ni3Si crystal phase or a Ni31Si12 crystalphase from the second polycrystalline silicon layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an example CMOSFET according to afirst embodiment;

FIG. 2 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an example process of manufacturingthe CMOSFET of the first embodiment;

FIG. 3 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing a process for manufacturing theCMOSFET of the first embodiment subsequent to the process shown in FIG.2;

FIG. 4 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing a process for manufacturing theCMOSFET of the first embodiment subsequent to the process shown in FIG.3;

FIG. 5 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an example CMOSFET according to asecond embodiment;

FIG. 6 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an example process of manufacturingthe CMOSFET of the second embodiment;

FIG. 7 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing a process for manufacturing theCMOSFET of the second embodiment subsequent to the process shown in FIG.6;

FIG. 8 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an example CMOSFET according to athird embodiment;

FIG. 9 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an example process of manufacturingthe CMOSFET of the third embodiment;

FIG. 10 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing a process for manufacturing theCMOSFET of the third embodiment subsequent to the process shown in FIG.9;

FIG. 11 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an example CMOSFET according to afourth embodiment;

FIG. 12 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an example process of manufacturingthe CMOSFET of the fourth embodiment;

FIG. 13 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing a process for manufacturing theCMOSFET of the fourth embodiment subsequent to the process shown in FIG.12;

FIG. 14 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing another example process ofmanufacturing the CMOSFET of the fourth embodiment;

FIG. 15 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing a process for manufacturing theCMOSFET of the fourth embodiment subsequent to the process shown in FIG.14;

FIG. 16 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing a process for manufacturing theCMOSFET of the fourth embodiment subsequent to the process shown in FIG.15;

FIG. 17 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing a process for manufacturing theCMOSFET of the fourth embodiment subsequent to the process shown in FIG.16;

FIG. 18 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an example CMOSFET according to afirst modification;

FIG. 19 is an exemplary bird's eye view showing an example CMOSFETaccording to a second modification;

FIG. 20 exemplary shows an X-ray diffraction spectrum of NiSi₂ phaseformed through heat treatment at 450° C. and 700° C.;

FIG. 21 exemplary shows a leak current characteristic of a MOS capacitorwhich uses as a gate electrode the NiSi₂ phase formed through heattreatment at 450° C. and 700° C.;

FIG. 22 exemplary shows a capacitance-voltage (C-V) characteristic ofthe MOS capacitor which uses as gate electrodes NiSi₂ phase formed atlow temperature and NiSi crystal phase of orthorhombic MnP type;

FIG. 23 exemplary shows a capacitance-voltage (C-V) characteristic ofthe MOS capacitor which uses NiSi, Ni₂Si, Ni₃₁Si₁₂, and Ni₃Si as gateelectrodes;

FIG. 24 exemplary shows a transmission electron microscope photographwhere a silicide gate electrode is formed as gate electrode of n-typeMIS transistor when Ti film and Ni film are formed on a polycrystallineSi according to embodiments without natural oxide film;

FIG. 25 exemplary shows a high-resolution image of an interface of thegate insulation film of FIG. 24;

FIG. 26 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an another example CMOSFET accordingto the third embodiment;

FIG. 27 is an exemplary manufacturing method of semiconductor deviceaccording to another example of CMOSFET according to the thirdembodiment;

FIG. 28 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing a process for manufacturing anotherexample of CMOSFET according to the third embodiment subsequent to theprocess shown in FIG. 27;

FIG. 29 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing a process for manufacturing anotherexample of CMOSFET according to the third embodiment subsequent to theprocess shown in FIG. 28;

FIG. 30 exemplary shows an another process for manufacturing anotherexample of CMOSFET according to the third embodiment;

FIG. 31 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an another process for manufacturinganother example of CMOSFET according to the third embodiment subsequentto the process shown in FIG. 30;

FIG. 32 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing an another process for manufacturinganother example of CMOSFET according to the third embodiment subsequentto the process shown in FIG. 31;

FIG. 33 is an exemplary diagram showing an oxide-film dependent propertyof V_(fb) calculated from a capacitance-voltage (C-V) characteristic ofgate electrode of n-type MIS transistor according to the secondembodiment;

FIG. 34 is an exemplary diagram showing a capacitance-voltage (C-V)characteristic where NiSi₂ is formed on N-doped silicate gate insulationfilm (HfSiON) and another capacitance-voltage (C-V) characteristic whereNi₃Si is formed on the N-doped silicate gate insulation film (HfSiON);

FIG. 35 is an exemplary diagram showing a relationship betweenmodulation amount of effective work function Φeff and a density ofimpurity on an interface in case that P is unevenly distributed to on aninterface by ion implantation of doping an impurity in each gateelectrode composed of Ni—Si after silicide electrode is formed; and

FIG. 36 is an exemplary diagrammatic cross-sectional view of anotherexample of CMOSFET according to the second embodiment in the directionof gate length.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will be described hereinbelow byreference to the drawings. Configurations common to the embodiments areassigned the same reference numerals, and repeated explanations thereofare omitted here for brevity. The drawings are exemplary schematicdiagrams for describing the invention and promoting comprehension of theinvention. Some of the drawings differ from an actual apparatus in termsof shape, dimensions, and proportions. The present invention can besubjected to engineering change, as appropriate, by taking into accountthe following descriptions and publicly-known techniques.

First Embodiment

An example CMOSFET according to a first embodiment will be described byreference to FIG. 1.

As shown in FIG. 1, a p-type impurity region (a p-well) and an n-typeimpurity region (an n-well) are formed in a p-type silicon substratethrough SiO₂ in an element isolation layer. Both gate insulation layers1 formed on both regions are silicon oxide films 1. The insulation layer1 may be formed to a thickness of 2 nm or less. A gate electrode 5 and agate electrode 6, each of which has a multilayer structure, are formedfrom Ni silicide on the respective gate insulation layers 1.

The Ni silicide gate electrode 5 on the p-well region is formed from acubic NiSi₂ crystal phase. All areas of the gate electrode 5 include apolycrystallineline layer whose crystal grains each assume a cubicCaF₂-type crystal structure and an Ni:Si composition of 1:2. As will bedescribed in detail later, the NiSi₂ crystal phase is formed at a lowtemperature, and hence the lattice constant thereof ranges from 5.39angstroms to 5.40 angstroms.

The Ni silicide gate electrode 6 on the n-well is formed from a cubicNi₃Si crystal phase. All areas of the gate electrode 6 include apolycrystallineline layer whose crystal grains assume a cubic AuCu₃-typecrystal structure and have a composition of Ni:Si=3:1. In addition tothe cubic Ni₃Si phase, the Ni silicide gate electrode 6 may be formedfrom a hexagonal Ni₃₁Si₁₂ phase.

In FIG. 1, all of the areas of the gate electrode 5 are formed from theNiSi₂ crystal phase. However, an NiSi₂ crystal phase may be formed of alayer in an interface area between the gate electrode 5 and the gateinsulation layer 1. The same also applies to the gate electrode 6.

The length (gate length) between the source and the drain of a gatestructure, consisting of the gate insulation layer 1 and the gateelectrodes 5, 6, may be 30 nm or less in connection with bothconductivity types.

A source region and a drain region, which correspond to an n-typehighly-doped impurity area, are formed in the p-well such that the gateinsulation layer 1 is sandwiched therebetween. An Ni silicide layer(NiSi layer) 3, which is a contact electrode, is formed on the sourceand drain regions. Thus, an N-type MIS transistor is fabricated in thep-type impurity region. In the meantime, a source region and a drainregion, which correspond to a p-type highly-doped impurity region, areformed on the n-type impurity region such that the gate insulation layer1 is sandwiched therebetween. As in the case of the n-type MIStransistor, the Ni silicide layer (NiSi layer) 3, which corresponds to acontact material, is formed on the source and drain regions. Thus, ap-type MIS transistor is fabricated in the n-type impurity region. Then-type MIS transistor and the p-type MIS transistor operatecomplementarily, to thus form a CMIS device.

In the embodiment, all gate electrodes of both conductivity types can beformed from Ni silicide of a single crystal structure. Gate electrodesof both conductivity types provided immediately above the gateinsulation film can be formed from Ni silicide having the same crystalstructure (single phase) in the entire interface region. By thusconfiguration, variations in threshold voltage become smaller than 0.05eV and allowable at the time of operation of the CMIS device. Thevariations are greatly smaller than variations in the effective workfunction (Φeff of K. Takahashi et al. which are of the order of about0.1 eV.

A single phase in the interface region is achieved, on condition thatcrystal grains of the electrodes contacting the interface of the gateinsulation film are analyzed with local electron diffraction of 5 nm orless, wherein crystal grains have different orientations but all thecrystal grains assume the same crystal structure, or a proportion ofanother phase to the main crystal phase is 1% or less.

In order to determine whether or not the gate electrode contacts theinsulation film, a sample is sliced at an angle perpendicular to theinterface between the gate electrode and the insulation film, and localelectron diffraction analysis is performed while the cross section isascertained by an image of a transmission electron microscope. Thethickness of the sample may be about one-half the size of the crystalgrain which is an object of analysis, so that crystal grains do nooverlap in the depthwise direction of the sample and the crystal grainscan be determined one by one.

A relationship between the crystal phase of Ni silicide and a crystalsystem is as follows:

Ni₃Si phase: cubic

Ni₃₁Si₁₂ phase: hexagonal

Ni₂Si phase: orthorhombic

NiSi phase: orthorhombic

NiSi₂ phase: cubic

In the case of an Ni silicide gate electrode, Φeff is known to greatlychange according to the Ni—Si composition of the gate electrode (see N.Biswas et al.). In reality, in the electrode where NiSi and NiSi₂ aremixed together, the effective work function Φeff exhibits a variation ofabout 0.1 eV including those described in K. Takahashi et al, the entirecontents of this reference being incorporated herein by reference.

Although detailed descriptions (see a manufacturing method of a first orthird embodiment) will be provided later, under the manufacturing methodof the embodiment, an NiSi₂ phase, which is negatively larger than anorthorhombic MnP-type NiSi phase in terms of heat of formation andthermodynamically stable, is formed as a first phase by an Nisilicidation reaction. Under the manufacturing method of the embodiment,a mixed phase consisting of the NiSi phase and the NiSi₂ phase is notformed in the interface between the gate electrode and the gateinsulation layer unless Ni is excessively present.

The gate electrode 5 of the n-type MIS transistor is formed from a cubicNiSi₂ crystal phase whose lattice constant is 5.39 angstroms to 5.40angstroms, and the lattice constant may be 5.393 angstroms or more. Thelattice constant is unique to the NiSi₂ crystal phase formed through aheat treatment process (e.g., 450° C.) which is lower than an ordinarytemperature (650° C. or higher) at which NiSi₂ is formed by an Ni/Siinterface reaction. This will be described in detail later by referenceto FIG. 20.

FIG. 20 shows an X-ray diffraction spectrum of the NiSi₂ phase formedthrough a heat treatment process of 450° C. in the present embodimentand an X-ray diffraction spectrum of the NiSi₂ phase formed through ahigh-temperature treatment process of 700° C.

These X-ray diffraction spectra are measured at room temperature by useof CuKα as the X-ray source and a θ/2θ method. Diffraction peaks ofcubic NiSi₂ are obtained under both conditions for formation.

Data obtained through XRD analysis correspond to a diffraction profilewhich is different from a profile obtained through above-described localelectron diffraction and reflects all crystal structures including theentire gate electrode and the Si substrate. In FIG. 20, only thediffraction peak of the NiSi₂ structure is detected as an electrodesilicide phase by the XRD profile, and hence the entire gate electrodeand the interface of the gate insulation film are understood to exhibita “single phase.”

All diffraction peaks of the NiSi₂ crystal phase of the presentembodiment appear at angles which are lower than those at which thediffraction peak appear when the crystal phase is formed through ahigh-temperature heat treatment process. A difference arises in latticeconstants; namely, the NiSi₂ crystal phase formed at a low temperaturein the present embodiment exhibits a lattice constant of 5.393 angstromsand the NiSi₂ crystal phase formed through high-temperature heattreatment of 700° C. exhibits a lattice constant of 5.381 angstroms. Thelattice constant of NiSi₂ formed at a low temperature is greater by0.2%. When compared with the lattice constant (5.406 angstroms) of aNiSi₂ phase of a bulk, the lattice constant obtained when the NiSi₂crystal phase is formed at a low temperature is closer to the latticeconstant of the bulk.

This is attributable to a difference in the temperatures at which thecrystal phase is formed. When the crystal phase is formed throughlow-temperature heat treatment, heat contraction is small, and hence adeviation from the lattice constant of the bulk becomes smaller.

Even when compared with the lattice constant (5.431 angstroms) of Si,the lattice constant of NiSi₂ formed at a low temperature is 0.6%, whichis smaller than the lattice constant (0.9%) of NiSi₂ formed throughhigh-temperature heat treatment. This signifies that application ofmechanical strain induced by a volumetric change, which arises duringsilicidation of polycrystalline Si during manufacturing processes, issmall. The mechanical strain applied to the gate insulation film and thegate sidewall, which are proximate to the gate electrode, is lessened,and the reliability of the transistor is enhanced. Further,deterioration of electron mobility, which would arise by application ofa compressive strain to a channel section, is prevented, wherebyhigh-speed operation of the device is considered to become possible.

FIG. 21 shows a leakage current characteristic of a MOS capacitor havingthe NiSi₂ phases, which have been formed by the respective methods, asgate electrodes. The employed gate insulation film is made of SiO₂ andhas a thickness of 7 nm. In the case of the NiSi₂ phase formed throughhigh-temperature heat treatment of 700° C., a leakage current isincreased by diffusion of Ni elements into the gate insulation filmthrough the high-temperature heat process. In contrast, in the case ofthe NiSi₂ phase formed at a low temperature of 450° C. in the presentembodiment, diffusion of Ni elements into the gate insulation film islessened because only low-temperature processes are performed. Damageattributable to diffusion of Ni elements does not arise, and a lowleakage current characteristic can be maintained.

FIG. 22 shows a capacitance-voltage (C-V) characteristic of the MOScapacitor employing the NiSi₂ electrode formed at a low temperature—andthe orthorhombic MnP-type NiSi electrode, which belong to theembodiment.

When compared with the case of an NiSi crystal phase electrode, a C-Vcharacteristic of the NiSi₂ crystal phase electrode formed at a lowtemperature shifts toward a negative voltage. By dependence of thethickness of a gate oxide film on the flat band voltage (Vfb) determinedfrom the C-V characteristic, a Vfb voltage achieved when the thicknessof an oxide film is zero is extracted through linear extrapolation. Theeffective work function Φeff of the electrode is extracted by the Fermilevel (4.92 eV) of the substrate determined from the concentration ofimpurity (1×10¹⁵ cm⁻³) of the Si substrate. In the case of the electrodeformed from the NiSi₂ crystal phase at a low temperature, the effectivework function Φeff is 4.54 eV, which is smaller than the effective workfunction Φeff of the NiSi crystal phase electrode (4.66 eV) by 0.12 eV.From this fact, it is understood that the operation threshold voltagecan be reduced as compared with the NiSi crystal phase electrode, by useof the NiSi₂ crystal phase electrode of the present invention for then-type MIS transistor. The device can be understood to be operated at alow voltage.

In the present embodiment, at the time of extraction of the effectivework function Φeff, the effective work function Φeff is assumed to beextracted by subtracting only fixed electric charges of the interfacebetween SiO₂ and the Si substrate from the dependence of Vfb on thethickness of an oxide film. Fixed charges are assumed not to be presentin the gate insulation film (SiO₂). However, in reality, fixed electriccharges are present in a film whose surface density is smaller than theamount of fixed charges in the interface by an order of magnitude ormore. The value of the effective work function Φeff extracted by thefixed charges includes an error of the order of about 0.05 eV. However,the effective work function Φeff of the NiSi₂ crystal phase remainssmaller than that of the NiSi crystal phase.

The gate electrode 6 of the p-type MIS transistor may employ a cubicNi₃Si phase or a hexagonal Ni₃₁Si₁₂ phase.

FIG. 23 shows a capacitance-voltage (C-V) characteristic of a MOScapacitor having a gate electrode of a NiSi crystal phase, acapacitance-voltage (C-V) characteristic of a MOS capacitor having agate electrode of a Ni₂Si crystal phase, a capacitance-voltage (C-V)characteristic of a MOS capacitor having a gate electrode of a Ni₃₁Si₁₂crystal phase, and a capacitance-voltage (C-V) characteristic of a MOScapacitor having a gate electrode of a Ni₃Si crystal phase.

The employed gate insulation film is SiO₂ and has a thickness of 10 nm.The crystal structure of each of the crystal phases is ascertained to bea single phase by XRD analysis. When compared with the case of an NiSicrystal phase electrode, the C-V characteristics of the respectivecrystal phases shift toward positive voltages. In the case of theorthorhombic Ni₂Si crystal phase electrode, the effective work functionΦeff extracted from the dependence of the Vfb voltage on the thicknessof the gate insulation film is 4.75 eV. In the case of the hexagonalNi₃₁Si₁₂ crystal phase electrode and the cubic Ni₃Si electrode, theeffective work function Φeff extracted from the dependence of the Vfbvoltage on the thickness of the gate insulation film is 4.85 eV. Thus,the effective work function Φeff becomes greater with an increase in theNi composition, to thus approach the valence band of Si. In the p-typeMIS transistor, as the value of the effective work function Φeff of theelectrode becomes closer to the valence band of Si, the operationthreshold voltage can be lower. Accordingly, the device can be operatedat a low voltage by use of a gate electrode of Ni silicide having alarge Ni composition, and a resultantly-yielded effect becomes greaterwith an increase in Ni composition. Consequently, as a result of use ofthe Ni₃Si crystal phase and the Ni₃₁Si₁₂ crystal phase for PMOS metal,the operation threshold value can be reduced by 0.2 eV as compared withthat achieved by use of the NiSi crystal phase.

When the threshold voltage required by the device is high, an Ni₂Sicrystal phase, or the like, may also be employed.

As a result of Ni silicide, whose crystal structure varies according toa conductivity type, being used for the gate electrode, operationvoltages for both conductivity types can be reduced, whereby a thresholdvoltage optimal for a device can be acquired.

The height of each of the gate electrodes 5, 6; namely, the thickness ofthe silicide film, may be 100 nm or less, and the height must be reducedwith shortening of the gate length. When the height is too high inrelation to the gate length, mechanical strength becomes insufficient,and the structure of the device cannot be maintained duringmanufacturing processes, thereby posing difficulty in manufacture of adevice. Typically, the height of the gate electrode may be two to threetimes the length of the gate. Even when the height is too low, the sheetresistance value required for the gate electrode fails to be attained,which in turn results in deterioration of the characteristic of thedevice. Therefore, a height required to achieve sheet resistance, whichis required according to the generation of the device technology, mustbe maintained, and at least a height of 20 nm or more is required.

Even in relation to the size of a crystal grain of silicide, the aboveconditions must be satisfied. Concurrently, in view of variations ineffective work function (Φeff), a particle size may be half or less thegate length.

In FIG. 1, a silicon oxide film is used as a gate insulation film.However, an insulation film material (a high dielectric insulation film)whose dielectric constant is higher than that of the silicon oxide filmmay be employed. For instance, the insulation film material includesSi₃N₄, Al₂O₃, Ta₂O₅, TiO₂, La₂O₅, CeO₂, ZrO₂, HfO₂, SrTiO₃, Pr₂O₃, orthe like. As in the case of Zr silicate or Hf silicate, a materialformed by mixing a silicon oxide with metal ions may be used.Alternatively, a combination of materials, such as LaAl oxide and thelike, may be used Material for transistors of respective generations maybe appropriately selected and used. Even in the following embodiment, asilicon oxide film is used as the gate insulation film. However,replacing the silicon oxide film with a high dielectric insulation filmmay be applied unless otherwise specified.

The gate insulation layer may include a layer including an Hf element,because the operation threshold voltage can be lowered further.

In this case, the effect of modulation of the effective work functionΦeff yielded as a result of formation of the NiSi₂ crystal phase becomesfurther greater. As a result of the NiSi₂ crystal phase formed at a lowtemperature being used for the NMOS gate electrode, the effective workfunction Φeff assumes a value of 4.3 eV, so that the threshold voltagecan be lowered further. This is attributable to Fermi-level pinningwhich is induced by Hf—Si bond arising in the interface between theelectrode and an Hf-based insulation film. As the Si composition of theelectrode-side interface becomes greater, the influence of pinningbecomes greater.

FIG. 34 is an exemplary diagram showing a capacitance-voltage (C-V)characteristic where NiSi₂ is formed on N-doped silicate gate insulationfilm (HfSiON) and another capacitance-voltage (C-V) characteristic whereNi₃Si is formed on the N-doped silicate gate insulation film (HfSiON).As shown in FIG. 34, a shift amount (width) of the characteristic islarger than that of the characteristic (on SiO₂) shown in FIG. 23 sothat an effective work function Φeff can be small by using NiSi2 grainphase on HfSiON.

In the case of the NiSi₂ crystal phase/Hf-based insulation film, thesurface density of Si in the NiSi₂ crystal phase is the same as thesurface density of polycrystalline Si, and hence an Hf—Si bond is formedat the same surface density. Specifically, in the case of the NiSi₂electrode, Fermi-level pinning which is as strong as that achieved inthe case of polycrystalline Si arises on SiO₂, and the effective workfunction has become smaller to only 4.54 eV. In contrast, on HfSiON,variations in work function greatly drop to 4.3 eV as in the case ofpolycrystalline Si.

This phenomenon becomes especially noticeable when the Hf composition is30% or more. However, even when the Hf composition is smaller than 30%,the work function is affected by the pinning phenomenon, so long as theHf—Si bond is present in the interface. The effective work function Φeffchanges from 4.54 eV (on SiO₂) to 4.3 eV (on HfSiON) according to thesurface density of the Hf—Si bond in the interface.

In contrast, in the case of the orthorhombic MnP-type NiSi phase, thesurface density of Si on the electrode side is about one-half thatachieved in the case of NiSi₂. Therefore, even in the case of aninsulation film having the same Hf composition, a pinning rate is halfthat achieved in the case of NiSi₂, and a drop in effective workfunction Φeff is small.

In the case of the Ni₃Si phase electrode having great Ni contentappropriate for PMOS metal, the amount of Si in the interface becomessmaller, and the influence of pinning becomes smaller. In the case ofthe Ni₃Si phase electrode, a difference between the effective workfunction Φeff achieved on SiO₂ and the effective work function Φeffachieved on the Ni₃Si phase electrode is 0.1 eV or less. Thus, aneffective work function Φeff essentially the same as that achieved onSiO₂ is realized. The Ni₃₁Si₁₂ phase exhibits essentially the samebehavior. Consequently, in a case where the NiSi₂ crystal phase is usedfor NMOS metal and where the Ni₃Si crystal phase and the Ni₃₁Si₁₂ phaseare used for PMOS metal, when the gate insulation layer including Hfelements is used, a particular decrease in the threshold voltages forrespective conductivity types can be achieved.

Using HfSiON, which is amorphous, for the gate insulation layer may beused.

The gate insulation layer may have an interface layer which is formedfrom SiO₂ and provided on the substrate side of the gate insulationlayer. The gate insulation layer may have an interface layer whichformed from SiO₂, SiON, SiN, or the like and provided on the gateelectrode side of the gate insulation layer. When the interface layer isformed on the gate electrode side of the gate insulation layer, the workfunction decrease effect of NiSi₂ due to the Fermi-level pinningphenomenon due to the Hf—Si bond becomes smaller with increasingthickness of the interface layer. From the practical viewpoint, thethickness of the interface may be 5 angstroms or less.

According to the embodiment, a work function which is superior in adecrease in the threshold voltage of a transistor fabricated on the bulksubstrate can be fulfilled. Hence, as shown in FIG. 1, the substrate maybe a bulk substrate.

Here, Si is used for the channel region. However, SiGe, Ge, and strainedsilicon, which are greater than Si in terms of mobility, may also beused.

First Embodiment Manufacturing Method: Implanting Ni Ions into an UpperPortion of the Gate

An example method for manufacturing the semiconductor device of thefirst embodiment will be described by reference to FIGS. 2 to 4.

A device isolation structure can be formed by a local oxidation methodor a shallow trench method and may also be of mesa type. Subsequently, ap-type impurity region (a p-well) and an n-type impurity region (ann-well) are formed by ion implantation.

Next, a thermal oxidation silicon film, which is to be used as a gateinsulation film, is formed on the surface of the silicon substrate. Whena high dielectric film is used for the gate insulation film, a metaloxide formed by the MOCVD method or the ALD method, or such a metaloxide doped with Si, N, or the like, is used in place of the silicon.

Subsequently, a polycrystalline silicon layer used as a gate electrodeis deposited to 50 nm, and a SiN cap layer is deposited thereon to 10 nmby decompression CVD. Patterning is performed by lithography, and theshape of the gate electrode is processed by anisotropic etching.

A heavily-doped shallow source-drain region (an extension region) ineach of the n-type MIS transistor and the p-type MIS transistor isformed by implantation of phosphor ions and boron ions. An elevatedsource-drain structure, which uses the selective epitaxial growth methodand can inhibit a short-channel effect as a device characteristic, mayalso be used for forming the source-drain diffused layer. Concurrentlywith formation of the elevated source-drain region, impurities may alsobe introduced.

A sidewall used for isolating the gate electrode from the source-drainregion is formed. Phosphor ions and boron ions are implanted at anacceleration voltage which is greater than the previously-employedacceleration voltage, to thus form a deep source-drain junction region.Ni is formed to 8 nm by sputtering, and the thus-formed film issubjected to heat treatment at 400° C., thereby forming an NiSi contactlayer in an upper portion of the source-drain region. Unreacted Ni inthe other region is selectively etched away by an H₂SO₄ solution, tothus selectively form NiSi in only the source-drain region.

Next, the SiN cap layer on the gate electrode is removed, and a siliconoxide film of an interlayer film is deposited by decompression CVD, andthe upper edge of the gate electrode is exposed by CMP(Chemical-Mechanical Polishing).

As shown in FIG. 2, Ni ions are implanted while the upper portions ofthe polycrystalline Si gate electrodes of both conductivity types remainexposed. The acceleration voltage is 10 keV, and the amount of ions tobe implanted is 5×10¹⁵ cm⁻² or more. Subsequently, the gate electrode issubjected to heat treatment for one hour at 400° C., whereby a cubicNiSi₂ crystal bulk of 10 nm or thereabouts is formed on the upperportion of the polycrystalline Si gate electrode.

As mentioned above, Ni ions are implanted into amorphous Si, and acrystal seed of NiSi₂ phase is known to be formed through subsequentheat treatment (see Non-Patent Document 4). In this case, long-hour heattreatment, which is as long as three hours, is employed for forming theNiSi₂ crystal seed from amorphous Si. Applying this method to theprocesses of manufacturing an LSI is not effective in terms ofproduction efficiency.

According to the manufacturing method of the present embodiment, thetime for heat treatment can be shortened by implanting Ni ions into apolycrystalline. The reason for this is that the NiSi₂ crystal phase andSi have the same cubic lattice structure and that a difference of 1% orless exists between the lattice constant of the NiSi₂ crystal phase andthe lattice constant of Si, and they are very close to each other. Atthe time of formation of the NiSi₂ crystal phase, a seed for growth canbe formed while taking polycrystalline Si of essentially-identicallattice structure as the point of origin.

Hence, the activation energy required to form a seed of NiSi₂ becomessmaller. Formation of a crystal seed is more likely to arise in a grainboundary which is more structurally unstable rather than in Si crystalgrains. Further, formation of a crystal seed is more accelerated by atriple point in the crystal grains. Specifically, energy becomesunstable at a point where a larger number of crystal grains overlap, andformation of a NiSi₂ crystal seed is accelerated. Therefore, the presentembodiment where Ni ions are implanted into polycrystalline Si is moresuitable for formation of crystal grains of NiSi₂ crystal phase in ashorter period of time.

Ni is grown to a film of 20 nm by sputtering. Subsequently, the film issubjected to low-temperature heat treatment at 500° C., whereby an NiSi₂crystal phase grows while taking the NiSi₂ bulk, which has already beenformed, as a seed for growth. The NiSi₂ crystal phase is formed at thegate electrodes of both conductivity types up to the interface of thegate insulation film (FIG. 3).

After removal of unreacted Ni from the device isolation SiO₂, only thep-type MIS transistor formed region is exposed by lithography, and then-type MIS transistor region is coated with a resist or a hard mask.Subsequently, Ni is again grown to a film of 50 nm by sputtering (FIG.4), and the film is subjected to heat treatment at 400° C., therebyforming only the gate electrode Ni₃Si of the p-type MIS transistor.Thus, the structure of the first embodiment can be manufactured (FIG.1).

According to the manufacturing method (FIGS. 2 to 4, and FIG. 1), amixed crystal phase of NiSi+NiSi₂, such as that described in connectionwith K. Takahashi et al., is not formed on the interface of the gateinsulation film unless the deposited film of the Ni layer 9 is madelarger in thickness than one-half the film of the polycrystalline Silayer 10. The reason for this is that, under the present manufacturingmethod, crystal of NiSi₂ phase, which is negatively larger than theorthorhombic MnP-type NiSi in terms of heat of formation; namely, astable phase, is formed in advance, and the orthorhombic MnP-type NiSi,which is more unstable, is not formed. The heat generated by the crystalof NiSi is 21.4 kcal/mol, and the heat generated by the crystal of NiSi₂is 22.5 kcal/mol.

When Si used for NiSi₂ in the vicinity of the interface is notsufficient with respect to the amount of Ni; namely, when Ni which isgreater than one-half the height of the polycrystalline Si gate has beendeposited, the phase that is finally formed is determined by the Ni—Sicomposition. For this reason, NiSi is formed in some portions, andvariations in the effective work function Φeff of the electrode becomegreater than 0.05 eV, as mentioned previously.

When the thickness of a deposited film of the Ni layer 9 is made smallerthan 5/18 the thickness of the polycrystalline Si layer 10, thethus-formed NiSi₂ phase does not reach the interface of the gateinsulation film, and the polycrystalline Si layer, which has not yetundergone silicidizing reaction, remains on the interface of the gateinsulation film. Therefore, formation of a metal gate electrode, whichis the object of the present invention, cannot be achieved.

Consequently, the thickness of a deposited film of an Ni layer may be5/18 to ½ the thickness of the polycrystalline Si layer.

The heat treatment process for generating an NiSi₂ crystal nucleus inthe polycrystalline silicon layer requires a temperature ranging from300° C. to 800° C. When the temperature is lower than 300° C., the NiSi₂crystal nucleus fails to be formed. In contrast, when the temperature ishigher than 800° C., a steep impurity profile of a heavily-dopedimpurity layer formed in the source-drain region cannot be maintained,which in turn leads to deterioration of the ON-OFF characteristic of thedevice.

Although the heat treatment process depends on temperature as well, theheat treatment process may be performed from 10 seconds to one hour.When the process is performed longer than one hour, there may arise afear of an increase in manufacturing cost in terms of productivity. Whenthe process is performed less than 10 seconds, there may arise a fear ofan NiSi₂ crystal nucleus failing to sufficiently grow in some devices.

The atmosphere of the heat treatment process may be a nitrogenatmosphere.

The heat treatment process for causing the NiSi₂ crystal nucleus to growand to transform the polycrystalline silicon layer into the NiSi₂crystal phase requires a temperature from 300° C. to 600° C. When thetemperature is lower than 300° C., the growth rate of crystal grains islow, which in turn increases production cost. In contrast, when thetemperature is higher than 600° C., the formed NiSi₂ phase inflictsdamage to the gate insulation film, which in turn deteriorates thereliability of the device.

Although the heat treatment process depends on temperature as well, theheat treatment process may be performed for one hour or less. If theprocess is performed longer than one hour, manufacturing cost isincreased in terms of productivity.

The atmosphere of the heat treatment process may be a nitrogenatmosphere.

Second Embodiment Impurity-Segregated Layer

Differences between an example CMOSFET according to a second embodimentand the CMOSFET of the first embodiment will be described by referenceto FIG. 5.

FIG. 5 is a cross-sectional schematic view of the example CMOSFET of thesecond embodiment in the direction of gate length.

As shown in FIG. 5, a structural difference between the CMOSFET shown inFIG. 5 and that shown in FIG. 1 lies in that one layer or less, which isdoped with impurities, is present on the interface between the gateelectrode and the gate insulation film in relation to the gateelectrodes of both conductivity types. P is unevenly distributed in atleast the first layer within the interface region between the gateelectrode 5 and the gate insulation layer 1 of the n-type MIStransistor, and the concentration of P is smaller than 1×10¹⁶ cm⁻². B(boron) is unevenly distributed in the interface region between the gateelectrode 6 and the gate insulation layer 1 of the p-type MIStransistor, and the concentration of B is smaller than 1×10¹⁶ cm⁻².

P is unevenly distributed to on the part, facing the electrode 5, of theinterface between the gate electrode 5 and the gate insulation layer 1of the n-type MIS transistor, to thus form an electrical dipole whichinduces positive charges on the part, facing the gate insulation film,of the interface. The effective work function Φeff continuouslydecreases with an increase in the concentration of P. However, thecontinuous decrease of the effective work function Φeff is for the casewhere the surface density of P forms one layer or less. The modulationeffect becomes saturated when the surface density has exceeded onelayer. The reason for this is that the modulation effect of Φeff isattributable to formation of an interface dipole.

FIG. 35 is an exemplary diagram showing a relationship betweenmodulation amount of effective work function Φeff and a density ofimpurity on an interface in case that P is unevenly distributed to on aninterface by ion implantation of doping an impurity in each gateelectrode composed of Ni—Si after silicide electrode is formed. Thedensity of impurity is quantitatively evaluated by SIMS analysis. Theeffective of the modulation of NiSi2 electrode due to the impurity islarger that of NiSi or Ni2Si, so that the modulation width of theeffective work function Φeff due to P can be a maximum of about 1.0 eV(for a case where a P-segregated layer forms one layer). Therefore, theeffective work function Φeff of the gate electrode of the n-type MIStransistor having the NiSi₂ structure as a result of segregation of P onthe interface becomes smaller by an interface uneven distributed amount4.5×10¹⁴ cm⁻² than that achieved when P is not present (NiSi₂: 4.54 eV),whereby the effective work function Φeff corresponding to the edge (Ec)of a conduction band of Si is implemented. Specifically, a minimum of4.15 eV is achieved. This value corresponds to the value of Φeff of thegate electrode optimal to a bulk-type high-speed-operation n-type MIStransistor.

FIG. 33 is an exemplary diagram showing an oxide-film dependent propertyof V_(fb) calculated from a capacitance-voltage (C-V) characteristic ofgate electrode of n-type MIS transistor according to the secondembodiment. A work function of NiSi2 is 4.54 ev without doping P.However, the work function of NiSi2 is 4.15 eV when P is doped by ionimplantation as shown in FIGS. 6 and 7. The ion implantation will bedescribed later.

Meanwhile, in the p-type MIS transistor, as a result of B beingsegregated on the interface, the Φeff value becomes greater, by amaximum of 0.4 eV, than the Φeff (4.85 eV) of Ni₃Si, which is achievedwhen B is not unevenly distributed. The reason for this is that theinterface dipole is modulated in a direction opposite that achieved inthe case of P. Another reason is that the segregated position of P is onthe electrode side of the interface between the electrode and the gateinsulation film; and that B is segregated on the part, facing the gateinsulation layer 1, of the interface. In relation to the distribution ofelectric charges in the interface, when compared with the case where thegate electrode is not doped, the negative electric charges are inducedon the part, facing the gate insulation film, of the interface by the Belements segregated in the first layer of the insulation-film-side ofthe interface, thereby forming a dipole oriented in the oppositedirection. As a result, the effective work function Φeff correspondingto the end (Ev) of the valence band of Si is fulfilled. As in the caseof segregation of P, the amount of modulation of Φeff increases inproportion to the surface density of B on the interface within theregion where B forms one layer or less. When B has formed one layer, theeffect becomes saturated. The maximum amount of modulation is 0.4 eV orthereabouts, and the effective work function Φeff increases up to 5.25eV. This value of the effective work function Φeff is essentially thesame as that achieved by the heavily-doped p-type polycrystalline Sielectrode, and is the value of the effective work function Φeff optimalfor a bulk-type high-speed operation p-type MIS transistor. When thepreviously-described HfSiON film or HfO₂ is used as the gate insulationfilm, any of these impurities diffuses in large amounts into theinsulation film and is not segregated on the interface. Hence, theabove-mentioned impurity modulation effect cannot be obtained. The SiO₂interface layer is placed in the upper portion of the HfSiON layer,whereby impurities are segregated on the interface between the gateelectrode and the interface layer, and the modulation effect due toimpurities is obtained.

When the CMIS device simultaneously has the gate electrode structures ofboth conductivity types, high-speed operation of the CMIS device becomespossible. It is better to adjust doping levels of P and B in accordancewith the operation threshold voltage required by the device. Forinstance, in the case of a low-power-consumption device, there is anecessity for increasing a threshold voltage and decreasing an OFFleakage current. Therefore, the doping level of impurities in theinterface must be set to a low level.

Elements used for doping the interface between the gate electrode andthe insulation film are not limited to P and B. When non-metal elementswhose electronegativity is greater than that of Ni and that of Si areused, control of the work function performed by addition of impuritiesis further facilitated. Especially, Sb and As are segregated on thepart, facing the gate electrode, of the interface, and yield a largeeffect of decreasing the effective work function Φeff, as in the case ofP. Sb and As are additional elements suitable for an n-type transistor.

Even when the additional impurities are segregated on the second layeror subsequent layers on the same side of the interface, the influence ofsegregation on the modulation effect is small. When the impurities aresegregated on the electrode-side of the interface, the impurities areblocked by free electrons of the electrode. Even when the impurities aresegregated on the insulation-film-side of the interface, electricaldipoles are isotropically formed, and the dipoles cancel each other.Meanwhile, when identical elements are segregated on the respectivesides of the interface, the effects of the resultant dipoles cancel eachother, whereupon the modulation effect of the effective work functionΦeff becomes smaller.

In the case of any of the elements, the segregation coefficient of theelement achieved in Ni silicide differs from the segregation coefficientof the element achieved in the gate insulation film. The elements arechiefly segregated in either the Ni silicide or the gate insulationfilm, and a value close to the previously-described maximum modulationwidth is obtained. Further, the additional elements are doped in thematrix of an electrode material or the matrix of an insulation filmmaterial. A layered structure having the property of a bulk ofadditional impurity elements should never be acquired. Typically, theadditional elements may be formed into five or fewer monolayers. Thereason for this is that, in the case of five monolayers or more, theadditional elements do not exhibit the effect of the dipole; and thatthe effective work function Φeff is determined by a vacuum work functionof the additional element layer, which is beyond the gist of the presentinvention.

A low-acceleration SIMS analysis method, which is applied to a substrateside, or photoelectron spectroscopy (XPS), is effective as the techniquefor measuring surface density of the segregated impurities. Especially,the status of impurities can be clarified by use of XPS, so that adetermination can be made as to whether the impurities are distributedin a gate electrode or in the insulation film.

As shown in FIG. 36, a predetermined effective work function Φeff can beobtained even though B is segregated on the interface in a gateelectrode of p-type MIS transistor by using NiSi₂ phase as well asn-type MIS transistor, since, as shown in FIG. 35, modulation effectiveis large in NiSi₂ due to the effective of segregated impurities. When adensity of B segregated on an insulation film side of the interface isadjusted to be about 6.5×10¹⁴ cm⁻², the predetermined effective workfunction Φeff can be 5.2 eV, and a high-speed operation of the p-typetransistor with low-threshold value can be made. Accordingly, CMISdevice can operate at high-speed. As shown in FIG. 35, when the impuritydensity on the interface is larger, the effective work function Φeffbecomes minus. However, in case that the impurities (for example, B) aresegregated on gate insulation film side of the interface, the code ofthe effective work function is inverted. Accordingly, the larger thevalue of the effective work function Φeff is, the larger the impuritydensity on the interface is.

Second Embodiment Manufacturing Method 1: Snow-Plow Method

Differences between one example process for manufacturing thesemiconductor device of the second embodiment and the process formanufacturing the semiconductor device of the first embodiment will bedescribed.

An example technique for forming the P-segregated layer and theB-segregated layer will be described. First, B or P impurities are alsointroduced simultaneously into the gate electrode during the ionimplantation operation, which is performed for formation of thesource-drain regions, without use of an SiN cap on the gate electrode.Subsequently, by the “snow-plow effect” achieved during a silicidationreaction, the impurities are segregated on the part, facing the gateelectrode, of the interface.

Any conditions may be employed as the conditions for ion implantation,so long as the conditions conform to those employed in the case ofimplantation of ions into the Ni silicide electrode and infliction ofdamage to the gate insulation layer can be avoided.

Second Embodiment Manufacturing Method 2: Ion Implantation Method)

Differences between another example process for manufacturing thesemiconductor device of the second embodiment and the process formanufacturing the semiconductor device of the first embodiment will bedescribed, by reference to FIGS. 6 and 7.

Subsequent to the process shown in FIG. 1, P is implanted at 5 keV to aconcentration of 1×10¹⁶ cm⁻² while only the region—where the n-type MIStransistor is fabricated—is exposed, (FIG. 6). By the same method, B isimplanted at 1 keV to a concentration of 1×10¹⁶ cm⁻² while only theregion—where the p-type MIS transistor is fabricated—is exposed (FIG.7).

Subsequently, P and B, which have been implanted into the respectivegate electrodes 5, 6 by one-hour heat treatment at 500° C., diffuse agrain boundary of the polycrystallineline Ni silicide layer, and aresegregated on the interface of the gate insulation film 1. Thus, thestructure shown in FIG. 5 can be manufactured.

Conditions for implanting B and P ions into the gate electrode are notlimited to those mentioned above. Arbitrary conditions may alternativelybe employed, so long as the acceleration voltage has lowered to such anextent that no damage is inflicted on the gate insulation film by ionradiation. Alternatively, ion implantation and heat treatment may beperformed while being separated into multistages. The essentialrequirement for a typical acceleration voltage used for implanting ionsis to fulfill conditions of an average distance range of ions fallinginto a region from the upper edge of the gate electrode to two-thirdsthe height of the gate. Further, the essential requirement for heattreatment is also to fulfill conditions of implanted elementssufficiently diffusing to the interface between the electrode and thegate insulation film according to the depth of implantation.

The temperature of heat treatment may range from 300° C. to 500° C. Whenthe temperature is lower than 300° C., the diffusion rate of Ni is slow,and sufficient diffusion of Ni involves consumption of much time,thereby deteriorating productivity. The temperature never exceeds 600°C. If the temperature exceeds 600° C., Ni diffuses into the gateinsulation film, thereby increasing a gate leakage current. In anextreme case, a short circuit arises between the gate electrode and thechannel region.

Depending on the heat of heat treatment, the heat treatment process maybe performed within the range of 10 seconds to one hour. If the heattreatment is performed longer than one hour, productivity will bedeteriorated, and manufacturing cost may be increased. In contrast, whenthe heat treatment is performed shorter than 10 seconds, there may arisea fear of NiSi₂ crystal nucleus failing to sufficiently grow in somedevices.

The atmosphere of the heat treatment process may be a nitrogenatmosphere.

The rate at which B diffuses into the Ni silicide film by way of thegrain boundary is 10 times or more the rate at which B diffuses into thepolycrystalline Si. For this reason, in relation to formation of aninterfacial segregated layer of B, when ion implantation is employedafter formation of Ni₃Si, B is efficiently segregated on the interface,and the amount of Φeff modulation becomes greater.

Third Embodiment TiSi₂ Upper Layer

Differences between an example CMOSFET according to a third embodimentand that of the second embodiment will be described by reference to FIG.8.

FIG. 8 is a cross-sectional schematic view of the example CMOSFET of thethird embodiment in the direction of gate length.

As shown in FIG. 8, the structural difference between the CMOSFET of thepresent embodiment and its counterpart shown in FIG. 5 lies in thestructure of a gate electrode of the n-type MIS transistor. In otherrespects, the CMOSFET is structurally identical with its counterpartshown in FIG. 5. In relation to the structure of the electrode of then-type MIS transistor, a lower layer on the part, facing the gateinsulation film, of the interface is formed from a polycrystallinelinelayer (a cubic NiSi₂ crystal phase) where each of crystal grains has acubic crystal structure and a 1:2 Ni—Si composition, and an upper layerof the same is formed from an orthorhombic TiSi₂ crystal phase of C49type. The crystal structure of the gate electrode is orthorhombic C49type. P is unevenly distributed over the interface between the NiSi₂layer and the gate insulation film, as in the case of the embodimentshown in FIG. 5.

According to this structure, the structure of the interface between thegate electrode and the gate insulation film is analogous to thatdescribed in connection with the second embodiment, and yields the sameadvantage as that yielded by the second embodiment. Details aredescribed in connection with the manufacturing method. However, thestructure of the gate electrode of the present embodiment can also bemanufactured through the heat process for forming silicide at 500° C. orless, and the reliability of the device is not impaired.

The thickness of the TiSi₂ crystal phase layer may range from 4.6 nm to24 nm. As will be described later, when a Ti thin layer is formed withinthe above-thickness range, the TiSi₂ crystal phase assumes a thicknessfalling within this range.

In FIG. 8, impurity segregated layers 7, 8 are formed in response to thesecond embodiment. However, in the third embodiment and all embodimentsdescribed herein after, these layers may be omitted as in the case ofthe first embodiment.

Third Embodiment Manufacturing Method: Insertion of Ti Thin Layer

An example method for manufacturing a semiconductor device of the thirdembodiment will be described by reference to FIGS. 9 and 10.

The method is the same as the method described in connection with FirstEmbodiment—Manufacturing Method up to the process of exposing the upperend of the gate electrode by CMP (Chemical-Mechanical Polishing). In thepresent embodiment, the SiN cap layer is not formed on the gateelectrode. During implantation of P or B ions into the source-drainregion, P ions are simultaneously introduced into the gate electrode forthe case of the n-type MIS transistor, as well; and B ions aresimultaneously introduced into the gate electrode for the case of thep-type MIS transistor.

A Ti layer having a thickness of 4 nm is formed in only the n-type MIStransistor region by lithography. Subsequently, as shown in FIG. 9, Niis caused to grow to 15 nm by sputtering while upper portions of thepolycrystalline Si gate electrodes of both conductivity types areexposed.

Subsequently, the gate electrode of the n-type MIS transistor issubjected to a heat treatment process for one minute at 450° C., apolycrystallineline layer of cubic NiSi₂ crystal phase is formedimmediately above the gate insulation film, and an orthorhombic TiSi₂crystal phase of C49 type is formed on the polycrystallineline layer toabout 8 nm. A polycrystalline line layer of NiSi is formed on the gateelectrode in the p-type MIS transistor region to a thickness of 30 nm,and the polycrystalline Si layer is formed below the polycrystallinelinelayer of NiSi so as to contact the gate insulation film over an area ofabout 20 nm. At this time, P and B elements in the polycrystalline Silayer are segregated on the interface of the gate insulation film and onthe interface between NiSi and polycrystalline Si by the “Snow-Plow”effect.

Next, only the p-type MIS transistor region is exposed by lithography,and Ni is caused to grow to a thickness of 50 nm by sputtering (FIG.10).

By performing low-temperature heat treatment at 400° C., all the gateelectrodes of the p-type MIS transistor are formed into apolycrystallineline layer of Ni₃Si crystal phase. At that time, B inpolycrystalline Si is segregated on the interface of the gate insulationfilm by the snow-plow effect. The structure shown in FIG. 8 can bemanufactured by removing unreacted Ni.

According to this manufacturing method, the diffusion rate of Niachieved during interfacial reaction between Ni and Si can be controlledby inserting the Ti thin layer into the interface between Ni and Si.Consequently, an NiSi₂ crystal phase can be formed in the first phase ofthe reaction.

In this case, the amount of Ni entering Si within a period of unit timeis determined by two factors; namely, the thickness of a Ti film, andthe temperature of heat treatment. Conditions other than those mentionedabove raise no problems, so long as the NiSi₂ crystal phase is formed asthe first phase by the conditions. Even when an interface insertionlayer other than Ti is used, the interface insertion layer, such as Tior the like, may be used in an optimal thickness, so long as the layerexhibits the role of decreasing the entry rate of Ni as in the case ofthe embodiment.

When Ni silicide is formed, a native oxide film formed on a surface ofpolysilicon in the atmosphere is eliminated, since reduction power of Niis weak. When the native oxide film of the polysilicon is not completelyeliminated, a silicide reaction is nonuniform. Accordingly, variation ofcharacteristics between transistors is large.

FIG. 24 exemplary shows a transmission electron microscope photographwhere a silicide gate electrode is formed as gate electrode of n-typeMIS transistor when Ti film and Ni film are formed on a polycrystallineSi according to embodiments without an natural oxide film. The gateinsulation film is HfSiON. Ti is deposited on Polysilicon Si layer(thickness 100 nm) and Ni is continuously sputtered on Ti deposition.After sputtering Ni, a heat treatment is performed at 450° C. in Niatmosphere for one minute, so that NiSi₂ crystal phase (a cubic crystal)is formed.

FIG. 25 exemplary shows a high-resolution image of an interface of thegate insulation film of FIG. 24. NiSi2 phase is formed on an interfaceof the gate insulation film, since Ti is a metal with high reducingpower, and Ti can reduce the native oxide film easily, so that thesilicide reaction is advanced. In this case, as shown in FIG. 24, it isconfirmed by EDX (Energy Dispersive X-ray) analysis that Ti oxidation isformed on an electrode layer. By a producing method according to theembodiment, a silicide can be easily formed in an area where the nativeoxide film remains and the variation of characteristics betweentransistors can be restrained. The same effective can be obtained when ametal element that can reduce SiO₂ is used as an interface insertinglayer. The metal elements for the interface inserting layer are, forexample, Hf, Zr, Y, La, Er which have a larger negative energy that thatof SiO₂.

The thickness of the Ti thin layer may range from 2 nm to 10 nm. Whenthe thin layer exceeds 10 nm, Ni may fail to diffuse to the Si layer.When the Ti thin film is smaller than 2 nm, diffusion of Ni is too fast,and NiSi₂ cannot be formed as an initial layer.

The heat treatment process for forming the NiSi₂ crystal phase requiresa temperature of 300° to 600° C. When the temperature is lower than 300°C., the diffusion rate of Ni is slow, and diffusion of Ni involvesconsumption of much time, thereby deteriorating productivity. Incontrast, when the temperature is higher than 600° C., the formed NiSi₂phase inflicts damage on the gate insulation film, thereby degrading thereliability of the device.

The heat treatment process depends on the temperature of heat treatment,and may be performed within the range of 10 seconds to one hour. If theheat treatment is performed longer than one hour, manufacturing cost maybe increased. In contrast, when the heat treatment is performed shorterthan 10 seconds, there may arise a fear of NiSi₂ crystal nucleus failingto sufficiently grow in some devices.

The atmosphere of the heat treatment process may be a nitrogenatmosphere.

When the method of the present embodiment is used for forming thesource-drain region, a (111) facet is formed along the interface ofNiSi₂ and Si, and the interface becomes very rough (see O. Nakatsuka etal.). However, as a result of the present method being used for the gateelectrode as in the case of the present embodiment, the interface ofNiSi₂ becomes smooth along the interface of the gate insulation film onthe atomic level, and hence roughness does not arise.

Under this manufacturing method, since the NiSi₂ crystal phase is formedat low temperature, a mixed crystal phase including NiSi and NiSi₂ isnot formed along the interface between the gate electrode and theinsulation film as mentioned in K. Takahashi et al., unless excessive Niions intrude into the gate electrode. The ratio of the thickness of theNi layer to the thickness of the polycrystalline silicon layer may beadjusted to that employed for forming the NiSi₂ crystal phase, asmentioned previously. Specifically, the thickness of the Ni layer may beone-half or less the thickness of the polycrystalline silicon layer.

Under the present manufacturing method, a method of implanting ionsafter formation of the gate electrode of the NiSi₂ crystal phase and thegate electrode of the Ni₃Si crystal phase may also be used as a methodfor introducing impurities. Alternatively, the “snow-plow” effect andthe method for implanting ions after formation of an electrode may alsobe used in combination.

(Another Example of CMOSFET According to Third Embodiment)

FIG. 26 is an exemplary diagrammatic cross-sectional view in thedirection of gate length, showing another example of CMOSFET accordingto the third embodiment. A structure of gate electrode of the p-type MIStransistor is different from that of the gate electrode as shown in FIG.8. A structure except for the gate electrode is identical to thestructure as shown in FIG. 8. In FIG. 26, polycrystalline layerincluding a crystal grain each grain consisting of a cubic crystal asNi3Si crystal phase, as described above, is a layer under a gateinsulation film side. A layer above the polycrystalline layer is formedof TiSi2 crystal phase of orthorhombic crystal “C49 type.” The crystalstructure of the layer is C49 type of orthorhombic crystal. In FIG. 26as well as FIG. 8, B is segregated on an interface between a cubiccrystal as Ni3Si crystal phase and gate insulation film. According tothe embodiment, a height of gate electrode of p-type MIS transistor istwo or three times as large as that of gate electrode of n-type MIStransistor. According to the structure, a structure of interface betweengate electrode/gate insulation film is same as the structure as shown inFIG. 8. As described in producing method later, a structure of gateelectrode of the example can be produced by a heat process of forming asilicide below 500° C. and reliability of the device is not missed.

(Manufacturing Method of Another Example of CMOSFET According to ThirdEmbodiment)

A manufacturing method of another example of CMOSFET according to thethird embodiment is exemplary described herein after, by referring toFIGS. 27 and 28. The manufacturing method is same as that of the firstembodiment until a process of exposing upper end portion of the gateelectrode is performed by CMP (Chemical Mechanical Polishing). Herein, Bis doped in the gate electrode of p-type MIS transistor without formingSiN cap layer, or P is doped in the gate electrode of n-type MIStransistor at the same time of implantation of P or B ions into thesource-drain region. Then, Ti layer (4 nm) and Ni (15 nm) are sputteredin both types MIS transistor area. (refer to FIG. 27.) By heat treatment(at 450° C. for one minute), polycrystalline layer of cubic crystalNiSi2 crystal layer is formed above the gate insulation film in the gateelectrodes of both type MIS transistors. TiSi₂ crystal phase (8 nm) oforthorhombic crystal (C49 type) is formed on the polycrystalline layer.P or B of polycrystalline Si layer is segregated on the interface of thegate insulation film by the “Snow-Plow” effect.

After eliminating non-reactive Ni, p-type MIS transistor area is exposedby using lithography technology, and Ni (50 nm) is sputtered on thearea.

Then, a heat treatment at 400° C. is performed, and all polycrystallinelayers of a cubic crystal as NiSi2 crystal phase under a gate electrodeof p-type MIS transistor are changed into a polycrystalline layer ofNi₃Si crystal phase. A height of gate electrode of p-type transistor isabout 2 or 3 times as large as that of gate electrode of n-typetransistor. The structure as shown in FIG. 26 can be obtained afternon-reactive Ni is eliminated. According to the manufacturing method,TiSi2 crystal phase (C49 type) is formed on an upper portion of the gateelectrode of p-type MIS transistor. TiSi2 phase is stronger than Ni3Siin view of etching resistance with respect to a liquid solution ofsulfuric acid-hydrogen peroxide. By taking configuration of the exampleas describe above, when non-reactive Ni is eliminated, the liquidsolution of sulfuric acid-hydrogen peroxide can be used at the sametemperature, and the same amount thereof in both cases of formation ofNiSi2 and formation of Ni3Si. Accordingly, the manufacturing method canbe simple. According to the manufacturing method, an interface insertinglayer made of material except for Ti can be used for reducing dopingspeed of Ni. For example, TiN can be used as the interface insertinglayer with a predetermined thickness.

FIGS. 30 and 31 exemplary show another process for manufacturing anotherexample of CMOSFET according to the third embodiment. An another processmanufacturing another example of CMOSFET according to the thirdembodiment is identical to the manufacturing method as shown in FIGS. 27and 28 (as describe above) until an upper portion of the gate electrodeis exposed by CMP (Chemical Mechanical Polishing).

A polysilicon gate electrode of p-type MIS transistor is etched bylithography technology, and the height of the polysilicon gate electrodeis 18 nm. (Please refer to FIG. 30.)

Ti layer (4 nm) and Ni (15 nm) are sputtered on an MIS transistor areaof both type of MIS transistors. (Please refer to FIG. 31.) Then, a heattreatment (at 400° C. for one minute) is performed.

A polycrystalline layer of a cubic crystal of NiSi2 crystal phase isformed above the gate insulation film in a gate electrode of n-type MIStransistor. TiSi2 crystal phase of orthorhombic crystal (C49 type)(about 8 nm) is formed above the polycrystalline layer.

The under layer of the gate electrode of p-type MIS transistor is formedof a polycrystalline layer of Ni3Si crystal phase, and TiSi2 crystalphase of orthorhombic crystal (C49 type) (about 8 nm) is formed abovethe polycrystalline layer of Ni3Si crystal phase.

Ti layer functions only to adjust a diffusion speed of Ni. A structureand composition of Ni silicide is determined by a thickness of Ni filmrelative to a height of polysilicon gate electrode. P and B included inpolycrystalline Si layer are segregated on the interface of the gateinsulation film by the “Snow-Plow” effect.

By eliminating non-reactive Ni, a CMIS transistor which has samestructure of the structure as shown in FIG. 26 can be formed. (refer toFIG. 32) However, differently from FIG. 25, as shown in FIG. 32, aheight of p-type MIS transistor is smaller than that of n-type MIStransistor. the differences between both height is 10-30 nm. Thedifference is smaller that of FIG. 26. Accordingly, it is easy to formcontact plug of upper wiring. In the manufacturing method as shown inFIGS. 30 and 31, all processes including a formation process of Ni,lithography process, and a heat treatment of formation of silicideelectrode are performed only one time. Accordingly, the manufacturingmethod as shown in FIGS. 30, 31 is easier than the manufacturing methodas shown in FIGS. 27-29 so as to form the above structure.

The height of polysilicon gate electrode of p-type MIS transistor is notlimited at 18 nm, but can be made to form Ni3Si phase on all surface ofinterface of gate insulation film by forming Ni above. A formationthickness of Ni is in such a range that NiSi2 is formed on a wholeinterface of gate electrode of n-type transistor. In order to complywith the above range, a ratio of a height of polysilicon gate electrodeof n-type of MIS transistor with respect to a height of polysilicon gateelectrode of p-type of MIS transistor is larger than 0.16 and smallerthan 0.35. Herein, a height of both types is defined by subtracting athickness of polysilicon consumed by forming TiSi2 from a height ofpolysilicon gate before forming the silicide. Ni silicide phase of bothtype transistors having a predetermined structure can be formed from thesame Ni film by adjusting a thickness of Ni film appropriately in casethat the above-ratio is within the range above defined. In theembodiment, the thickness (8.8 nm) of polysilicon is consumed by Ti (4.4nm), so that the above-defined ratio is 0.22 (9.2 nm/41.2 nm) within theabove range. When p-type transistor is NiSi2, the above ratio is equalto or larger than 0.35, and is equal to or smaller than 0.50. Accordingto the manufacturing method,

In case that n-type MIS transistor and P-type MIS transistor, forexample, used as “SRAM circuit”, are arranged along a direction of gatewidth and that gate electrodes are continuously arranged, a compositionchange area of Ni silicide where compositions are changed in Ni-silicidearea on interface of both gate electrodes can be made small.The composition change area of Ni silicide particularly generates in aperiphery of edge of the interface of gate electrodes in case that Ni isselectively formed in a gate electrode area of either one type. However,an edge of Ni film is not generated in the embodiment.

According to another process for manufacturing another example ofCMOSFET according to the third embodiment, an interface inserting layermade of material except for Ti can be used for reducing doping speed ofNi. For example, TiN can be used as the interface inserting layer with apredetermined thickness.

Fourth Embodiment NiSi Upper Layer

Differences between an example CMOSFET according to a fourth embodimentand the CMOSFET of the second embodiment will be described by referenceto FIG. 11.

FIG. 1 is across-sectional schematic view of the example CMOSFET of thefourth embodiment in the direction of gate length.

As shown in FIG. 11, a difference between the CMOSFET of the presentembodiment and its counterpart shown in FIG. 5 lies in the structure ofthe electrode of the n-type MIS transistor. In other respects, theCMOSFETs are structurally identical with each other. In relation to thestructure of the electrode of the n-type MIS transistor, a lower layeron the part, facing the gate insulation film, of the interface is formedfrom a polycrystallineline layer (a cubic NiSi₂ crystal phase) wherecrystal grains have a cubic crystal structure and a 1:2 Ni—Sicomposition, and an upper layer of the same is formed from anorthorhombic NiSi crystal phase having a crystal structure oforthorhombic MnP type. P is unevenly distributed over the interfacebetween the NiSi₂ layer and the gate insulation film, as in the case ofthe embodiment shown in FIG. 5.

In relation to the structure of the present embodiment, the structure ofthe interface between the gate electrode and the gate insulation film isanalogous to its counterpart shown in FIG. 5, and the advantage of thestructure is also identical. The NiSi phase, which is lower inresistance than the NiSi₂ phase, is formed. Therefore, the sheetresistance value of the gate electrode of the n-type MIS transistor ismade lower than that of the gate electrode of the second embodiment, andthe device can operate at higher speed. Although detailed descriptionsare provided in connection with the manufacturing method, the structureof the gate electrode of the present embodiment can also be manufacturedthrough the heat process for forming silicide at a temperature of 500°C. or less, and the reliability of the device is not impaired.

In FIG. 11, the impurity segregated layers 7, 8 are formed in accordancewith the second embodiment. However, in the fourth embodiment, theselayers may be omitted as in the case of the first embodiment.

Fourth Embodiment Manufacturing Method 1: Gate Upper Layer Phase ChangeNiSi₂NiSi

An example method for manufacturing a semiconductor device of the fourthembodiment will be described by reference to FIGS. 12 and 13.

First, the structure shown in FIG. 5 is formed according to thepreviously-described manufacturing method. Subsequently, an Ni layer of5 nm is formed in only the n-type MIS transistor region through use oflithography (FIG. 12).

Subsequently, the structure is subjected to the heat process for oneminute at 400° C., whereby the phase of the upper portion of the gateelectrode of the n-type MIS transistor is transformed from the NiSi₂crystal phase to the NiSi crystal phase. Thus, the structure shown inFIG. 13 can be formed.

Even under the present manufacturing method, impurities may beintroduced after formation of the gate electrode of NiSi₂ and the gateelectrode of Ni₃Si, or by a combination thereof.

The specific resistance value of the NiSi crystal phase is about halfthat of the NiSi₂ crystal phase. As a result of the upper portion of thegate electrode of NiSi₂ crystal phase being transformed into the NiSicrystal phase, the resistance of the gate electrode can be reduced, andhigher-speed operation of the device can be implemented.

Fourth Embodiment Manufacturing Method 2: Implant Ni Ions into theMiddle of the Gate

An example process for manufacturing the semiconductor device of thefourth embodiment will be described by reference to FIGS. 14 to 17.

The method is identical with the previously-described method up to theprocess of exposing the upper end of the gate electrode by CMP(Chemical-Mechanical Polishing).

Like the case shown in FIG. 2, Ni ions are implanted while the upperportion of the polycrystalline Si gate electrodes of both conductivitytypes are exposed. In this case, the acceleration voltage is set to 30keV or thereabouts, whereby the peak depth of Ni ions comes to 20 nm orthereabouts from the surface of the polycrystalline Si electrode. Theamount of ions implanted is 5×10¹⁵ cm⁻² or more. At this time, the upperportion of the gate electrode assumes an amorphous structure, because ofdamage inflicted by ion implantation.

Subsequently, the structure is subjected to the heat process for 30minutes at 350° C., whereby NiSi₂ crystal bulks, which measure 10 nm orthereabouts and assume a CaF₂ structure, are formed at a depth of about20 nm in the polycrystalline Si gate electrode. An Ni film of 20 nm isformed by sputtering (FIG. 14). Subsequently, the film is subjected tolow-temperature heat treatment at 500° C. or less, whereby Ni diffusesinto Si, and an NiSi crystal phase is formed in an area which is shallowwith respect to the position 20 nm. Concurrently, in an area which isdeeper than the position (20 nm from the surface) where NiSi₂ crystalbulks are formed, NiSi₂ crystal grows while taking the previously-formedNiSi₂ bulks as the seed of growth, and an NiSi₂ crystal phase is formedup to the interface of the gate insulation film.

Subsequently, the crystal is subjected to lithography, to thus form anNi film of 25 nm in only the region where the p-type MIS transistor isfabricated (FIG. 15), and the film is subjected to heat treatment at400° C., thereby forming Ni₃Si in only the gate electrode of the p-typeMIS transistor.

After removal of unreacted Ni, only the region where the n-type MIStransistor is fabricated is exposed by lithography, and the p-type MIStransistor region is covered with a resist or a hard mask. In thisstate, P ions are implanted at 5 keV to a concentration of 1×10¹⁶ cm⁻²(FIG. 16). By the same method, only the region where the p-type MIStransistor is fabricated is exposed, and B ions are implanted at 1 keVto a concentration of 1×10¹⁶ cm⁻² (FIG. 17).

The B and P ions subsequently implanted into the gate electrode throughheat treatment at 400° C. for 30 minutes diffuse the crystal boundary ofthe polycrystallineline Ni silicide layer, and are segregated on theinterface of the gate insulation film. Thus, the structure shown in FIG.11 can be manufactured. Even under the manufacturing method, addition ofimpurities may be performed concurrently with implantation of ions intothe source-drain region.

(Modification)

The first through fourth embodiments have been described by reference toa planar semiconductor device on a bulk substrate. However, the first tofourth embodiments can also be applied to a planar semiconductor deviceon an SOI substrate or an Fin-type semiconductor device.

(First Modification: Planar Semiconductor Device on SOI Substrate)

An example CMOSFET according to a modification will be described byreference to FIG. 18.

As shown in FIG. 18, a CMIS device is fabricated on an SOI substrate.The structure of the CMIS device is identical with the structure shownin FIG. 1. The thickness of an Si active region of the SOI substratewhere the CMIS device is fabricated is 15 nm, and the present device isa so-called fully-depleted CMIS device.

In the fully-depleted device, the doping level of impurities in thechannel region of the substrate is low, and the channel region is fullydepleted. Accordingly, the effective work function Φeff of the gateelectrode required to realize high-speed operation of the device differsfrom that required for the bulk device. Specifically, in the case of thebulk device, the effective work function Φeff comes to the end of theforbidden band of Si. In the fully-depleted device, the effective workfunction Φeff for the gate electrodes of both conductivity types iscloser to Si-midgap by 0.2 eV. In the present embodiment, the NiSi₂crystal phase and the NiSi₃ crystal phase are used for the respectivegate electrodes, and the effective work functions Φeff of the crystalphases assume values optimal for high-speed operation of theperfectly-depleted device.

FIG. 18 is a view of a mode adaptive to the first embodiment. As amatter of course, the first modification may be of a mode adaptive toany of the second to fourth embodiments.

The gate electrodes of both conductivity types may be switched on theSOI substrate. By this structure, the operation threshold voltage isincreased by about 0.5 eV when compared with the operation thresholdvoltage achieved in the case shown in FIG. 18. This leads to a decreasein consumption of standby power during operation standby, and low powerconsumption of the CMIS device can be implemented by use of thisstructure.

(Second Modification: Fin-Type Semiconductor Device)

An example CMOSFET of the modification will be described by reference toFIG. 19.

As shown in FIG. 19, a buried oxide, which is a deposited silicon oxidefilm, is formed on a p-type silicon substrate. AF in structure, formingthe source-drain region of a transistor, is formed on the buried oxide.In an illustrated structure, the Fin structure corresponds to a stackedstructure consisting of a p-type Si layer and an SiN layer in the n-typeMIS transistor.

In the p-type MIS transistor, the Fin structure corresponds to a stackedstructure consisting of an n-type Si layer and an SiN layer. Further,the Fin structure can also be formed from a single Si layer or aninsulation layer other than SiN.

The gate electrodes 5, 6 are formed from Ni silicide so as to crossthese Fin structures, and a silicon oxide film—serving as a gateinsulation film 1—is formed in the contact interface. In the n-type MIStransistor, the gate electrode consisting of Ni silicide is apolycrystallineline film of NiSi₂ crystal phase, and the gate electrodeis a polycrystallineline film of Ni₃Si crystal phase in the p-type MIStransistor.

This structure corresponds to a so-called double gate MIS transistor,where an MIS transistor having a channel section is fabricated on eitherside surface portion of the Fin section. When a single Si layer is usedfor the Fin section, the upper portion of Fin also becomes a channelregion, so that a tri-gate MIS transistor is formed.

Although not illustrated, a source region and a drain region, bothbelonging to an n-type heavily-doped impurity region, are formed in thep-type Fin as a source-drain section such that a channel region issandwiched between the source and the drain. A source region and a drainregion, both belonging to a p-type heavily-doped impurity region, areformed in a Fin of n-type impurity. In a device element having athree-dimensional structure as described in connection with the secondmodification, extreme difficulty is encountered in rendering theheightwise doping level of impurities uniform. Accordingly, a Schottkysource-drain structure may also be adopted.

The second modification is an embodiment where the gate electrodeinterfacial structure shown in FIG. 1 is applied to the Fin-typefully-depleted transistor. The present embodiment is also directed tothe perfectly-depleted device as in the case of the first modification.Accordingly, the effective work function Φeff of the gate electrodes isoptimal for the high-speed operation CMIS device. By switching thestructures of the gate electrodes of both conductivity types, a CMISdevice of lower power consumption can also be implemented.

As mentioned above, the structure of the gate electrode interfaceaccording to the present invention can also be applied to a transistorof three-dimensional structure regardless of the transistor of planartype. In relation to the manufacturing method, the manufacturing methodfor planar type can be applied, so long as the method is optimized.

Although the present embodiment has used a double-gate MIS transistor ofFin structure, there can also be used a planar double gate CMIStransistor, a portrait double gate CMIS transistor, or another deviceelement of three-dimensional structure.

FIG. 19 is a view adaptive to the first embodiment. However, as a matterof course, the second modification may be adaptive to the second tofourth embodiments.

According to the embodiments, a semiconductor device includes smallvariations in threshold value, and a method for manufacturing the same.

Although the embodiments have been described thus far, the presentinvention is not limited to these embodiments. The present invention isliable to various alterations within the scope of gist of the presentinvention described in claims. Further, the present invention can bemodified in various manners at the practical stage within the scope ofthe gist of the invention. Moreover, the plurality of constituentelements described in the embodiments are combined, as appropriate,whereby various inventions can be created.

1. A semiconductor device comprising: a N-channel MIS transistorcomprising: a p-type semiconductor layer; a first gate insulation layerformed on the p-type semiconductor layer; a first gate electrode formedon the first gate insulation layer, the first gate electrode comprisinga crystal phase including a cubic crystal of NiSi2 which has a latticeconstant of 5.39 angstroms to 5.40 angstroms; and a first source-drainregion formed in the p-type semiconductor layer where the first gateelectrode is sandwiched along a direction of gate length.
 2. Asemiconductor device comprising: a substrate; an N-channel MIStransistor comprising: a p-type semiconductor layer formed on thesubstrate; a first gate insulation layer formed on the p-typesemiconductor layer; a first gate electrode formed on the first gateinsulation layer, the first gate electrode comprising a crystal phaseincluding a cubic crystal of NiSi2 which has a lattice constant of 5.39angstroms to 5.40 angstroms; and a first source-drain region formed inthe p-type semiconductor layer where the first gate electrode issandwiched along a direction of gate length; a P-channel MIS transistorcomprising: an n-type semiconductor layer formed on the substrate; asecond gate insulation layer formed on the n-type semiconductor layer; asecond gate electrode formed on the second gate insulation layer, thesecond gate electrode comprising a crystal phase including at least oneof a cubic crystal of Ni3Si or a hexagonal crystal of Ni31Si12; and asecond source-drain region formed in the n-type semiconductor layerwhere the second gate electrode sandwiched along a direction of gatelength.
 3. The semiconductor device according to claim 1, wherein thecrystal phase of cubic crystal of NiSi2 is polycrystal and a singlephase.
 4. The semiconductor device according to claim 1, comprising; afirst element segregation layer where at least one of a phosphor,arsenic, and antimony are segregated formed on a first-electrode-side ofan interface between the first gate electrode and the first gateinsulation layer; and a second element segregation layer where a boronis segregated formed on second-gate-insulation-layer-side of aninterface between the second gate electrode and the second gateinsulation layer.
 5. The semiconductor device according to claim 1,wherein the first gate electrode comprises: an upper layer formed from acrystal phase including an orthorhombic crystal of TiSi2; and a lowerlayer formed from the crystal phase including the cubic crystal ofNiSi2.
 6. The semiconductor device according to claim 5, wherein theupper layer of the first gate electrode has a thickness of 4.6 nm to 24nm.
 7. The semiconductor device according to claim 1, wherein the firstgate electrode comprises: an upper layer formed from a crystal phaseincluding an orthorhombic crystal of NiSi; and a lower layer formed fromthe crystal phase including the cubic crystal of NiSi2.
 8. Thesemiconductor device according to claim 1, wherein the gate insulationlayer has a layer including Hf.
 9. The semiconductor device according toclaim 1, wherein the gate insulation layer has a layer formed fromHfSiON.
 10. The semiconductor device according to claim 2, wherein thesubstrate is a bulk substrate. 11.-20. (canceled)